Chip package structure and manufacturing method thereof

ABSTRACT

The present invention provides a chip package structure and the manufacturing method thereof, which affords higher heat dissipation efficiency and is suitable to fabricate the stack type package structure with a higher integration. The chip package structure comprises a carrier, at least a chip, a heat sink and a mold compound. The chip is disposed on the carrier, while the bonding pads of the chip are electrically connected to the leads of the carrier. The heat sink is disposed over the chip and includes at least a body and a plurality of connecting portions. The connecting portions are disposed around a periphery of the body and are electrically connected to the leads. By using a specially designed heat sink, the chip package structure can afford better heat dissipation and be suitable to form stack type package structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application Ser.no. 92132104, filed on Nov. 17, 2003.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a package structure and themanufacturing method thereof. More particularly, the present inventionrelates to a stacked chip package structure and the manufacturing methodthereof.

2. Description of Related Art

Following the quick progress in the fabrication of integrated circuits,the design of the electrical products becomes more complex andhigh-speed and multi-function chips are developed. As the integration ofICs keeps increasing and the layout of the high-speed semiconductordevices becomes dense, more heat is generated by the semiconductordevice per unit area in a certain period. Thus, it is important for thedesign of semiconductor devices to consider the heat dissipation issue,in order to prevent damages to the electronic devices or the chips.

Conventionally, a metal heat dissipation plate, for dissipating heatresulting from the operation of the chip, is disposed on the outersurface of the mold compound, so that the heat dissipation plate canhelp dissipate heat generated from the operation of the chip into theexternal environment outside the mold compound.

FIG. 1 is a cross-sectional view of a prior quad flat no-lead (QFN)package structure. Referring to FIG. 1, the QFN package structure 100includes a leadframe 110, a chip (or die) 120, a plurality of wires 130,a heat sink 140 and a mold compound 150. The leadframe 110 includes adie pad 112 and a plurality of leads 114. The chip 120 has an activesurface 120 a with a plurality of bonding pads 122 disposed on theactive surface 120 a, while the chip 120 is fixed to the die pad 112.Each bonding pad 122 is electrically connected to one of the leads 114through the wire 160 by wire bonding.

As shown in FIG. 1, the heat sink 140 is disposed on the mold compound150. The shape of the heat sink can be varied depending on therequirements of heat dissipation and layout design. The mold compound150 is filled within the space between the heat sink 140 and theleadframe 110, covering the leads 114, the bonding pads 122 and thewires 130. As the chip 120 is in operation, the produced heat can bedissipated by the heat sink 140 through the mold compound 150.

For electronic modules (such as DRAMs) with multiple chip packages, thechip packages are usually stacked up and connected in parallel toprovide better electrical properties and faster transmission speed.Hence, the size and the area of the package structure are reduced.Although the heat sink may assist heat dissipation, multiple wires areneeded to connect the chip package structures for the stack type packagestructure. Therefore, the costs, the complexity and the uncertainty ofthe fabrication processes are increased.

SUMMARY OF THE INVENTION

The present invention provides a chip package structure and themanufacturing method thereof, which affords higher heat dissipationefficiency and is suitable to fabricate the stack type package structurewith a higher integration.

Accordingly, the present invention provides a chip package structure,comprising a carrier, at least a chip, a heat sink and a mold compound.The chip is disposed on the carrier, while the bonding pads of the chipare electrically connected to the leads of the carrier. The heat sink isdisposed over the chip and includes at least a body and a plurality ofconnecting portions. The connecting portions are disposed around aperiphery of the body and are electrically connected to the leads.

The aforementioned package structure can employ wiring bondingtechnology or flip chip technology to connect the chip to the carrier.The heat sink can be integrally formed as one piece or separatelyformed.

As embodied and broadly described herein, the present invention providesa manufacturing method for the chip package structure, the methodcomprising the following steps: providing a carrier having a pluralityof leads; disposing a chip on the carrier, so that the chip iselectrically connected to the carrier; providing a heat sink including abody, a plurality connecting portions and a plurality of protrusions,while each connecting portion is connected to the body through aprotrusion; disposing the heat sink above the chip and connecting theconnecting portions to the leads; filling a mold compound into a spaceenclosed by the heat sink and the carrier; and removing the protrusionsof the heat sink, so that the connecting portions are separated from thebody.

Because the heat sink is disposed over the chip and a mold compound isformed between the chip and the heat sink, heat generated by the chipcan be dissipated by the heat sink via the mold compound. In thisinvention, the connecting portions of the heat sink are disposed arounda periphery of the body and connected to the leads. By using a speciallydesigned heat sink, the chip package structure can afford better heatdissipation and be suitable to form stack type package structures.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a cross-sectional view of a prior QFN package structure.

FIGS. 2A–2F are display cross-sectional views showing the manufacturingprocess steps of a QFN package structure according to the firstpreferred embodiment of the present invention.

FIG. 3 is a display cross-sectional view showing a stack type chippackage structure according to one preferred embodiment of the presentinvention.

FIG. 4 is a cross-sectional view showing a QFN package structureaccording to the second preferred embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a QFN package structureaccording to the third preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A–2F are display cross-sectional views showing the manufacturingprocess steps of a QFN package structure according to the firstpreferred embodiment of the present invention. Referring to FIG. 2A, aleadframe 210 used as a carrier is provided. The leadframe 210 includesa die pad 212 and a plurality of leads 214. As shown in FIG. 2B, a chip220 is disposed on the die pad 212. The chip 220 has an active surface220 a and a plurality of bonding pads 222 on the active surface 220 a.Referring to FIG. 2C, each of the leads 214 is connected to one bondingpad 222 through a plurality of wires 230 by, for example, wire bonding.

Referring to FIG. 2D, a heat sink (or heat dissipation plate) 240 isprovided. The heat sink 240 is made of a conductive material and has abody 242, a plurality of connecting portions 244 and a plurality ofprotrusions 246. The heat sink may be in a spider shape from the topview, for example. The connecting portions 244 are disposed around theedge of the body 242 and are connected to the body 242 and theprotrusions 246. As the heat sink 240 is disposed above the chip 220,the connecting portions 244 are electrically connected to the leads 214through a conductive glue layer (not shown), for example. As shown inFIG. 2E, a mold compound 250 is filled into the space between theleadframe 210 and the heat sink 240. The mold compound 250 covers thechip 220. Later, as shown in FIG. 2F, a polishing process is performedto remove the protrusions 246 of the heat sink 240, so that a pluralityof openings 240 a is formed in the upper flat portion of the heat sink240. By forming the openings 240 a, the connecting portions 244 areseparated from the body 242, while each connecting portion 244 isseparated from one another. Each connecting portion 244 includes anupper flat portion 244 a and a lower supporting portion 244 b. Hence,the QFN chip package structure 200 is obtained. It is noted that themold compound 250 in the above structure is disposed within and insideof the heat sink 240. However, the mold compound may be disposed outsideof the connecting portions 244 and covers the connecting portions 244for protecting the connecting portions 244.

For the above QFN package structure, the heat sink 240 above the chip220 helps dissipate heat. Through the mold compound, the heat producedfrom the operation of the chip can be transferred to the heat sink andthen be dissipated to the outside environment by the heat sink. In thedesign of the heat sink, after removing the protrusions to form theopenings, the connecting portions 244 are separated from the body 242but still are electrically connected to the leads 214. Hence, the upperflat portions 244 a of the connecting portions 244 can be considered ascontact pads electrically connected to the leads. When applied to form astack type chip package structure, the upper flat portions 244 a (ascontact pads) of the connecting portions 244 can be directly connectedto the leads of another chip package structure, without using extrawires.

According to this invention, the QFN chip package structure can be usedto form a stack type chip package structure. As shown in FIG. 3, thestack type chip package structure 300 includes a first chip packagestructure 300 a and a second chip package structure 300 b. Thestructures and elements of the first and second chip package structures300 a/300 b are similar or identical to the QFN chip package structuredescribed above, and will not be illustrated in details. The first leads314 a of the first chip package structure 300 a are electricallyconnected to the second leads 314 b of the second chip package structure300 b via the second connecting portions 344 b of the second chippackage structure 300 b. The first leads 314 a can be connected with thesecond connecting portions 344 b through a conductive solder material ora conductive adhesive, for example. Therefore, the first chip 320 a iselectrically connected to the second chip 320 b. However, the stack typechip package structure is not limited to the double-stacked structuredescribed above, and can be in multiple layered or in other forms.

For the above QFN package structure, except for wire bonding, flip chiptechnology may be applied to connect the chip and the leadframe. FIG. 4is a cross-sectional view showing a QFN package structure according tothe second preferred embodiment of the present invention. In the QFNchip package structure 400, the chip 420 is electrically connected tothe leadframe 410 by flip chip technology. Conductive bumps 430electrically and physically connects the leads 414 of the leadframe 410and the bonding pads 422 of the chip 420. The mold compound 450 isdisposed between the leadframe 410 and the heat sink 440, and covers thechip 420. Moreover, a plurality of thermal conductive blocks 432 aredisposed between the active surface 420 a of the chip 420 and the diepad 412 of the leadframe 410. The thermal conductive blocks 432 can beformed with the conductive bumps in the same process, for example. Theconductive bumps 430 are disposed between the leads 414 of the leadframe410 and the bonding pads 422 of the chip 420 for electrically connectingthe leadframe 410 and the chip 420. On the other hand, the thermalconductive blocks 432 are disposed between the active surface 420 a ofthe chip 420 and the die pad 412 of the leadframe 410 for heatdissipation purposes. With this arrangement, the thermal conductiveblocks 432 help transfer heat from the active surface 420 a of the chipto the die pad 412, and heat can then be dissipated to the outsideenvironment by the die pad 412.

FIG. 5 is a cross-sectional view showing a QFN package structureaccording to the third preferred embodiment of the present invention. Inthe QFN chip package structure 500, the chip 520 is electricallyconnected to the carrier (the leadframe) 510 by flip chip technology.Instead of forming the thermal conductive blocks, a thermal conductivelayer 560 is formed between the chip 520 and the die pad 512. Since thecontact area of the thermal conductive layer is even broader than thetotal contact areas of the thermal conductive blocks, better heatdissipation can thus be provided.

Accordingly, the present invention provides QFN chip package structuresand the manufacturing method thereof. By using a specially designed heatsink, the QFN package structure can afford better heat dissipation andbe suitable to form stack type package structures. Although theleadframe is used as the carrier in the above embodiments, othercarriers can be employed.

In conclusion, the present invention provides a quad flat no-lead (QFN)package structure and a fabrication process thereof, with improvedelectrical properties and faster transmission speed. Moreover, this QFNpackage structure is suitable to form stack type package structures, sothat the size and the area of the package structure can be minimized.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A chip package structure, comprising: a carrier having a carryingsurface, wherein the carrier comprises a plurality of conductive leads;a chip, disposed on the carrying surface of the carrier and having anactive surface, wherein a plurality of bonding pads is disposed on theactive surface and is electrically connected to the conductive leads; aheat sink, disposed above the chip, wherein the heat sink includes abody and a plurality of connecting portions and the connecting portionsare disposed around a periphery of the body but are not connected to thebody, and wherein lower portions of the connecting portions that arefarther away from the body are electrically connected to the conductiveleads; and a mold compound covering the chip and filling up a spaceenclosed by the carrier and the heat sink.
 2. The package structure asclaimed in claim 1, further comprising a plurality of wires, whereineach of the wire electrically connects one of the bonding pads and oneof the conductive leads.
 3. The package structure as claimed in claim 1,wherein the carrier includes a leadframe.
 4. The package structure asclaimed in claim 1, wherein the heat sink is integrally formed.
 5. Thepackage structure as claimed in claim 1, further comprising a conductiveglue layer, wherein the connecting portions and the conductive leads areelectrically connected through the conductive glue layer.
 6. The packagestructure as claimed in claim 1, further comprising a plurality ofbumps, wherein each of the bumps electrically connects one of thebonding pads and one of the conductive leads.
 7. The package structureas claimed in claim 1, further comprising a thermal conductive layer,wherein the thermal conductive layer is disposed between a die pad ofthe carrier and the chip.
 8. The package structure as claimed in claim1, further comprising a plurality of thermal conductive blocks, whereinthe thermal conductive blocks are disposed between a die pad of thecarrier and the chip.
 9. A stack type chip package structure,comprising: a first chip package structure comprising a first carrierhaving a plurality of first leads, a first chip disposed on the firstcarrier and having a plurality of first bonding pads electricallyconnected to the first leads, a first heat sink disposed above the firstchip and having a first body and a plurality of first connectingportions, and a first mold compound covering the first chip and filledbetween the first carrier and the first heat sink, wherein the firstconnecting portions of the first heat sink are disposed around aperiphery of the first body but are not connected to the first body, andthe first connecting portions are electrically connected to the firstleads; and a second chip package structure comprising a second carrierhaving a plurality of second leads, a second chip disposed on the secondcarrier and having a plurality of second bonding pads electricallyconnected to the second leads, a second heat sink disposed above thesecond chip and having a second body and a plurality of secondconnecting portions, and a second mold compound covering the second chipand filled between the second carrier and the second heat sink, whereinthe second connecting portions of the second heat sink are disposedaround a periphery of the second body but are not connected to thesecond body, and the second connecting portions are electricallyconnected to the second leads, and wherein the first leads of the firstchip package structure are electrically connected to the second leads ofthe second chip package structure via the second connecting portions ofthe second heat sink of the second chip package structure, so that thefirst chip is electrically connected to the second chip.
 10. The packagestructure as claimed in claim 9, wherein the first chip packagestructure further comprises a plurality of wires, wherein each of thewire electrically connects one of the first bonding pads and one of thefirst leads.
 11. The package structure as claimed in claim 9, whereinthe second chip package structure further comprises a plurality ofwires, wherein each of the wire electrically connects one of the secondbonding pads and one of the second leads.
 12. The package structure asclaimed in claim 9, wherein the first carrier includes a leadframe. 13.The package structure as claimed in claim 9, wherein the second carrierincludes a leadframe.
 14. The package structure as claimed in claim 9,wherein the first chip package structure further comprises a pluralityof bumps, wherein each of the bumps electrically connects one of thefirst bonding pads and one of the first leads.
 15. The package structureas claimed in claim 9, wherein the second chip package structure furthercomprises a plurality of bumps, wherein each of the bumps electricallyconnects one of the second bonding pads and one of the second leads. 16.The package structure as claimed in claim 9, wherein the first chippackage structure further comprises a thermal conductive layer, whereinthe thermal conductive layer is disposed between a die pad of the firstcarrier and the first chip.
 17. The package structure as claimed inclaim 9, wherein the second chip package structure further comprises athermal conductive layer, wherein the thermal conductive layer isdisposed between a die pad of the second carrier and the second chip.18. The package structure as claimed in claim 9, wherein the first chippackage structure further comprises a plurality of thermal conductiveblocks, wherein the thermal conductive blocks are disposed between a diepad of the first carrier and the first chip.
 19. The package structureas claimed in claim 9, wherein the second chip package structure furthercomprises a plurality of thermal conductive blocks, wherein the thermalconductive blocks are disposed between a die pad of the second carrierand the second chip.